Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type, or a combination thereof.
One type of such split gate type memory cell has separated first (source) and second (drain) regions formed in a semiconductor substrate with a channel region therebetween. A floating gate is insulated from the substrate and is disposed over a first portion of the channel. A control gate is insulated from the substrate and is spaced apart from the floating gate and is disposed over a second portion of the channel, different from the first portion. Such a cell is exemplified by U.S. Pat. No. 5,029,130. Methods for making such a type cell is also disclosed in the aforementioned patent.
One of the problems facing the manufacturability of semiconductor floating gate memory cell arrays has been the alignment of the various components such as source, drain, control gate, and floating gate. As the design rule of integration of semiconductor processing decreases, reducing the smallest lithographic feature, the need for precise alignment becomes more critical. Alignment of various parts also determines the yield of the manufacturing of the semiconductor products.
Self-alignment is well known in the art. Self-alignment refers to the act of processing one or more steps involving one or more materials such that the features are automatically aligned with respect to one another in that step processing. Accordingly, self alignment minimizes the number of masking steps necessary to form memory cell structures, and enhances the ability to scale such structures down to smaller dimensions.
U.S. Pat. No. 6,429,075 discloses a method of self-aligning the floating gate to the control gate by forming the floating gate underneath insulation material, forming insulation material around exposed ends of the floating gate, and forming the control gate as a spacer of conductive material that is disposed laterally adjacent to and over the floating gate.
The formation of spacers is well known in the art, and includes depositing a material over the contour of a structure, followed by an anisotropic etch process, whereby the deposited material is removed from horizontal surfaces of the structure, while the material remains largely intact on vertically oriented surfaces of the structure. Ideally, spacers are formed with rounded upper surfaces. In reality, spacer upper surfaces can include pits or trenches that collect processing materials during subsequent processing steps, and can result in the formation of “stringers” or other deformations of the spacer structure. Deformed spacers can render the resulting memory cell inoperative (e.g. punch through problems because ion implantation used to form source/drain penetrates through the control gate).
To prevent the formation of spacer surface pits or trenches, the anisotropic etch is prolonged during spacer formation, which is known as “over-etch”. The problem with over-etch is that more of the spacer material is removed than is desired, and the resulting spacer structure can be too small. As the design rules are decreased to reduce the overall size of the memory cells, there is little if any margin to allow for spacer over-etch and still provide a functional memory cell structure.